RISC-V /Debug /Match Control (32-bit mcontrol)

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Interpret as Match Control (32-bit mcontrol)

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (load)load 0 (store)store 0 (execute)execute 0 (u)u0 (s)s0 (m)m0 (equal)match0 (disabled)chain 0 (breakpoint)action0 (any)sizelo 0 (before)timing 0 (address)select 0 (hit)hit 0sizehi 0maskmax0 (dmode)dmode 0type

select=address, timing=before, action=breakpoint, match=equal, chain=disabled, sizelo=any

Description

This register provides access to the trigger selected by {csr-tselect}. The reset values listed here apply to every underlying trigger.

This register is accessible as {csr-tdata1} when {tdata1-type} is 2. This trigger type is deprecated. It is included for backward compatibility with version 0.13.

đź“Ś NOTE

This trigger type only supports a subset of features of the newer {csr-mcontrol6}. It is expected that new implementations will not support this trigger type and that new debuggers will not use it if {csr-mcontrol6} is available.

Address and data trigger implementation are heavily dependent on how the processor core is implemented. To accommodate various implementations, execute, load, and store address/data triggers may fire at whatever point in time is most convenient for the implementation. The debugger may request specific timings as described in {mcontrol-timing}. tab:hwbp_timing suggests timings for the best user experience.

A chain of triggers that don’t all have the same {mcontrol-timing} value will never fire. That means to implement the suggestions in tab:hwbp_timing, both timings should be supported on load address triggers that can be chained with a load data trigger.

The Privileged Spec says that breakpoint exceptions that occur on instruction fetches, loads, or stores update the tval CSR with either zero or the faulting virtual address. The faulting virtual address for an mcontrol trigger with {mcontrol-action}=0 is the address being accessed and which caused that trigger to fire. If multiple mcontrol triggers are chained then the faulting virtual address is the address which caused any of the chained triggers to fire.

If {csr-textra32} or {csr-textra64} are implemented for this trigger, it only matches when the conditions set there are satisfied.

Fields

load

When set, the trigger fires on the virtual address or data of any load.

store

When set, the trigger fires on the virtual address or data of any store.

execute

When set, the trigger fires on the virtual address or opcode of an instruction that is executed.

u

When set, enable this trigger in U-mode. This bit is hard-wired to 0 if the hart does not support U-mode.

s

When set, enable this trigger in S/HS-mode. This bit is hard-wired to 0 if the hart does not support S-mode.

m

When set, enable this trigger in M-mode.

match

0 (equal): Matches when any compare value equals {csr-tdata2}.

1 (napot): Matches when the top M bits of any compare value match the top M bits of {csr-tdata2}. M is XLEN-1 minus the index of the least-significant bit containing 0 in {csr-tdata2}. Debuggers should only write values to {csr-tdata2} such that M + {mcontrol-maskmax} ≥ XLEN and M > 0, otherwise it’s undefined on what conditions the trigger will match.

2 (ge): Matches when any compare value is greater than (unsigned) or equal to {csr-tdata2}.

3 (lt): Matches when any compare value is less than (unsigned) {csr-tdata2}.

4 (mask low): Matches when latexmath:[$\frac{XLEN}{2}-{1:0}] of any compare value equals latexmath:[$\frac{XLEN}{2}-{1:0}] of {csr-tdata2} after latexmath:[$\frac{XLEN}{2}-{1:0}] of the compare value is ANDed with XLEN-1:latexmath:[$\frac{XLEN}{2}$] of {csr-tdata2}.

5 (mask high): Matches when XLEN-1:latexmath:[$\frac{XLEN}{2}$] of any compare value equals latexmath:[$\frac{XLEN}{2}-{1:0}] of {csr-tdata2} after XLEN-1:latexmath:[$\frac{XLEN}{2}$] of the compare value is ANDed with XLEN-1:latexmath:[$\frac{XLEN}{2}$] of {csr-tdata2}.

8 (not equal): Matches when {mcontrol-match}=0 would not match.

9 (not napot): Matches when {mcontrol-match}=1 would not match.

12 (not mask low): Matches when {mcontrol-match}=4 would not match.

13 (not mask high): Matches when {mcontrol-match}=5 would not match.

chain

0 (disabled): When this trigger matches, the configured action is taken.

1 (enabled): While this trigger does not match, it prevents the trigger with the next index from matching.

action

The action to take when the trigger fires. The values are explained in tab:action.

0 (breakpoint):

1 (debug mode):

2 (trace on):

3 (trace off):

4 (trace notify):

8 (external0):

9 (external1):

sizelo

This field contains the 2 low bits of the access size. The high bits come from {mcontrol-sizehi}. The combined value is interpreted as follows:

0 (any): The trigger will attempt to match against an access of any size. The behavior is only well-defined if {mcontrol-select}=0, or if the access size is XLEN.

1 (8bit): The trigger will only match against 8-bit memory accesses.

2 (16bit): The trigger will only match against 16-bit memory accesses or execution of 16-bit instructions.

3 (32bit): The trigger will only match against 32-bit memory accesses or execution of 32-bit instructions.

4 (48bit): The trigger will only match against execution of 48-bit instructions.

5 (64bit): The trigger will only match against 64-bit memory accesses or execution of 64-bit instructions.

6 (80bit): The trigger will only match against execution of 80-bit instructions.

7 (96bit): The trigger will only match against execution of 96-bit instructions.

8 (112bit): The trigger will only match against execution of 112-bit instructions.

9 (128bit): The trigger will only match against 128-bit memory accesses or execution of 128-bit instructions.

timing

0 (before): The action for this trigger will be taken just before the instruction that triggered it is retired, but after all preceding instructions are retired. xepc or {csr-dpc} (depending on {mcontrol-action}) must be set to the virtual address of the instruction that matched.

If this is combined with {mcontrol-load} and {mcontrol-select}=1 then a memory access will be performed (including any side effects of performing such an access) even though the load will not update its destination register. Debuggers should consider this when setting such breakpoints on, for example, memory-mapped I/O addresses.

If an instruction matches this trigger and the instruction performs multiple memory accesses, it is UNSPECIFIED which memory accesses have completed before the trigger fires.

1 (after): The action for this trigger will be taken after the instruction that triggered it is retired. It should be taken before the next instruction is retired, but it is better to implement triggers imprecisely than to not implement them at all. xepc or {csr-dpc} (depending on {mcontrol-action}) must be set to the virtual address of the next instruction that must be executed to preserve the program flow.

select

This bit determines the contents of the XLEN-bit compare values.

0 (address): There is at least one compare value and it contains the lowest virtual address of the access. It is recommended that there are additional compare values for the other accessed virtual addresses. (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000 and the other addresses are 0x4001, 0x4002, and 0x4003.)

1 (data): There is exactly one compare value and it contains the data value loaded or stored, or the instruction executed. Any bits beyond the size of the data access will contain 0.

hit

If this bit is implemented then it must become set when this trigger fires and may become set when this trigger matches. The trigger’s user can set or clear it at any time. It is used to determine which trigger(s) matched. If the bit is not implemented, it is always 0 and writing it has no effect.

maskmax

Specifies the largest naturally aligned powers-of-two (NAPOT) range supported by the hardware when {mcontrol-match} is 1. The value is the logarithm base 2 of the number of bytes in that range. A value of 0 indicates {mcontrol-match} 1 is not supported. A value of 63 corresponds to the maximum NAPOT range, which is 2^63^ bytes in size.

sizehi

This field only exists when XLEN is at least 64. It contains the 2 high bits of the access size. The low bits come from {mcontrol-sizelo}. See {mcontrol-sizelo} for how this is used.

dmode
type

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